1. Field of the Invention
The invention described herein relates generally to integrated circuit testing, and more particularly, to memory array built in self testers for random access memory arrays with redundancy circuits for failure relief.
2. Description of Background
In order to test RAM macros, e.g., SRAM macros with redundant elements for failure relief, by means of Array Built-In Self Test (ABIST), the data from the array is usually compared to expected data generated by the self test ABIST function. To this end, the ABIST circuitry is used for test vector generation of address and data, and subsequent comparison circuitry is used to provide a bit wise fail vector corresponding to each of the data-outs of the memory array, or device under test. This additional circuitry is either embedded in the SRAM or provided in surrounding logic.
This fail vector, or the situation of determining that a failure has occurred, is then processed to establish if the failure can be repaired using the redundant elements/circuitry of the memory array under test. This processing for establishing the redundant element configuration for failure relief is traditionally handled “off-chip” by various test equipment apparatus and peripheral computer software analysis of the component under test as described in U.S. Pat. No. 6,594,788 entitled “Method of Analyzing a Relief of Failure Cell in a Memory and Memory Testing Apparatus Having a Failure Relief Analyzer Using the Method” issued on Jul. 15, 2003, and U.S. Pat. No. 5,790,559, entitled “Semiconductor Memory Testing Apparatus” issued on Aug. 4, 1998.
Similarly, apparatus involving large memory storage (e.g., equal to the target memory array) can be used to support memory IC testing with redundant circuits as described in U.S. Pat. No. 5,337,318 issued to Tsukakoshi et al. Tsukakoshi recites a method for processing and determining repairability of the target memory array.
The memory array redundant elements can be provided in a plurality of configurations, usually based on the overall size of the memory array macro, addressing configuration, and the number of data outs provided. Memory arrays can be viewed as three dimensional binary storage elements: considering a row dimension and a column dimension to describe an array of memory cells, and this array of cells can be replicated to provide for a plurality of data input/output bits, each composed of the two dimensional array of memory cells. To generalize the categories for background purposes here, DRAM macros (due to the high number of memory bits) will usually contain a plurality of column and word addressable redundant elements. That is, both spare rows of memory cells and spare columns of memory cells are provided for relief of manufacturing defects, each spanning the total number of data input/output pins for the memory array.
SRAM macros are generally smaller in total size and, due to the larger memory cell requirements, are generally provided fewer spare elements, although these elements may be provided as both column and row addressable elements. In fact, due to generally fewer column addressable elements of a high speed SRAM macro, column addressable spare or redundant elements become costly in terms of the overall number of memory array cells. Therefore, a secondary scheme of column spare elements can be provided by providing spare data inputs/outputs or some fraction of a data bit group of cells, as disclosed by Davis et al. in patent application Ser. No. 10/814,719, entitled “Skip Over Redundancy Decode with Very Low Overhead” which was filed on Mar. 31, 2004, assigned to the Assignees of the present invention and is incorporated herein by reference in its entirety. A more general case is to reduce the number of repair actions, or to limit the redundant elements to a single dimension of row addressable or column addressable elements only.
The support for two dimensional redundancy allocation is growing more complex for SRAM memory arrays with increased data I/O widths (i.e., number of data bits into and out of the array) and the increased number of repair actions desired for yield improvement on high speed, high density SRAM product.
In addition, redundant elements in the SRAM macros are not restricted to just the address or data bit dimensions, but are now increasingly utilizing the column addressing and data bit architecture of the SRAM. The thrust here has been to keep the size of the redundant element as small as possible for low overhead and high area efficiency, while increasing the overall number of repair actions available for failure relief of the memory array.
Therefore, it is becoming increasingly important to determine with more specificity where a failure has occurred in a memory array, for subsequent processing and generation of a failure relief condition of the memory array. A clear need exists to reduce the complexity of the logic and process to establish a repairable configuration of a memory array with redundant elements, and thereby reduce the test time and cost required. There is also a clear need to reduce the circuit overhead of the test compare, as well as the processing for establishment of the redundant element configuration for failure relief of memory arrays with redundant circuits.